New Method Quantifies Hysteresis in 2D-MOSFETs, Aiding Future Designs
Researchers from the University of California, Berkeley, have introduced a precise method to quantify hysteresis width in 2D-MOSFETs. This standardized scheme aims to improve understanding and comparison of device stability across various materials, aiding in predicting performance for future ultra-thin designs.
Hysteresis in 2D-material transistors has been challenging to understand due to inconsistent measurement conditions and fragmented knowledge of underlying mechanisms. A team led by Prof. Scott M. Kim and graduate student Sidney Foreman has developed a diagnostic tool using hysteresis measurements to assess stability and project performance of MOSFETs based on 2D materials.
The new measurement scheme uses a triangular staircase signal and considers the frequency and temperature dependence of hysteresis width. It reveals that higher frequencies and temperatures reduce hysteresis. Additionally, the active energy region near the channel and gate within the insulator significantly influences hysteresis in these transistors.
Scientists are also working on compact models for 2D field-effect transistors, accounting for charge distribution and capacitance within the device. Defect dynamics, including charge trapping and defect occupation governed by Fermi-Dirac statistics, dominate hysteresis in 2D transistors. Quantum capacitance also significantly impacts device behavior and requires accurate modeling.
The innovative measurement scheme promises to enhance understanding and comparison of hysteresis in 2D-material transistors. As research continues, exploring ferroelectric materials like hafnium oxide and strontium titanate may lead to novel memory devices and performance enhancements in transistors.
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